The invention relates to switch arbitration, for example for use in high performance switches.
The efficiency of a high performance switch for computer buses, for example for PCI Express or InfiniBand, is dependent on the chosen arbitration scheme that orders the internal packet transfers from the input ports (transmitters) to the output ports (receivers).
A switch has a number of resources, such as ports, buffers and internal busses. These resources will often depend on each other (e.g., the usage of some resources typically requires the availability of others). At a certain time, a buffer at each input port typically holds packets to several destinations, while packets to a certain destination are held in different input buffers. If an input buffer has a single read port, and this read port is busy feeding data to one output port, another output port might have to wait idle until the read port of the input buffer becomes available.
Having an arbitration scheme that orders the packet transfers in a way so that most of the resources of the switch are in use, will make it possible to transfer the highest number of packets at the same time. This will result in a highly efficient switch. On the other hand a scheme where a great number of the resources are unused for longer periods of time, give low switch efficiency.
The present invention seeks to provide efficient arbitration for a switch system.